1. Field of the Invention
The present invention is directed to a semiconductor integrated circuit, and particularly, it is applied to a memory on which an error correcting code (ECC) circuit is utilized.
2. Description of the Related Art
Miniaturization of elements with progress of semiconductor device technology has caused, for example, a reduction in a storage node capacity of a cell that stores data. Consequently, a soft error of data has become a big problem.
Thus, in recent years, an ECC circuit has frequently been utilized as countermeasures of such a soft error.
The memory on which the ECC circuit is utilized has a section for storing data bits as normal data and a section for storing code bits used to detect errors. A data bit error is detected based on a code bit. If an error is detected, a bit in which the error occurs is further checked to execute error correction.
Error correction and detection capabilities of the ECC circuit are decided by the number of code bits. Generally, most of ECC circuits have 1-bit error correction functions and 2-bit error detection functions. In this case, single error correction-double error detection (SEC-DED) codes are used as code bits.
Meanwhile, in the system LSI chip, the built-in self test (BIST) circuit is often utilized in order to test defectiveness/nondefectiveness of the memory. The BIST circuit functions to write/read a test pattern in/from the memory, and to detect a defect of a cell by comparing read-out data as a memory output with written data as an expected value.
As the test pattern, a so-called marching pattern is widely used by taking a Stack-at-fault rate, testing time, a circuit size etc., into consideration.
A test algorithm (basic operation) by the marching pattern is as follows.
(1) First, background data are written in all the cells (all the addresses) that constitute the memory. As the background data, for example, repeated data [1010 . . . ], [0101 . . . ], identical data [1111 . . . ], [0000 . . . ] etc., are used.
(2) Next, a testing target address (first address) is specified, and data is read out of the testing target address. Then, the read-out data is compared with the background data (expected value) to test the testing target address.
(3) Subsequently, inverted data of the background data is written/read in/from the testing target address. For example, the inverted data becomes [0101 . . . ] if the background data is [1010 . . . ], and [0000 . . . ] if the background data is [1111 . . . ]. The read-out data is then compared with the inverted data (expected value) to test the testing target address.
Subsequently, the operations (2) and (3) are repeated while the testing target addresses are changed. When all the addresses are tested, the testing operation is finished.
FIG. 1 shows an example of a conventional semiconductor integrated circuit comprising a memory on which an ECC circuit is utilized and a BIST circuit.
A data bit as normal data and a code bit for error detection are stored in a memory cell array 11. During testing, a data bit is generated at, e.g., the BIST circuit 13, and a code bit is generated at, e.g., the ECC circuit 12 based on the data bit.
The read-out data as the memory output is subjected to error correction by the ECC circuit 12, and then transferred to the BIST circuit 13. Assuming that the ECC circuit 12 has a 1-bit error correction function, even if there is a 1-bit defect (cell failure or the like) in the testing target address, the defect can be corrected. Thus, such a defect can be permitted.
That is, in the BIST circuit 13, since the read-out data that has been subjected to the error correction by the ECC circuit 12 is compared with the background data (expected value), both data are equal to each other when there is a defect not exceeding one bit in the testing target address, and a result of the testing determines a product to be nondefective.
On the other hand, when there is a defect of two bits or more (cell failure or the like) in the testing target address, this defect cannot be corrected by the ECC circuit 12 that has the 1-bit error correction function. Thus, in the BIST circuit 13, complete coincidence is not determined between the read-out data and the background data (expected value), and a result of the testing determines a product to be defective.
However, in the conventional test carried out by generating the marching pattern at the BIST circuit 13, a defective bit may not be accurately detected in the testing target address. In this case, there is a problem that a defective product may be determined as nondefective.
This problem is specifically described below.
It is assumed that an ECC circuit that has a 1-bit error correction function and a 2-bit error detection function is utilized in a memory to be tested.
To begin with, consideration is given to a case in which [1010 . . . ] is written as background data in all the addresses of the memory.
As shown in FIG. 2, testing target addresses 0, 1, 2, . . . 7 are specified after the background data is written, and 8-bit data is read out of the testing target addresses 0, 1, 2, . . . 7. It is assumed here that among the testing target addresses 0, 1, 2, . . . 7, a bit of the address 5 is a Stack-at-one fault (always “1”) and a bit of the address 7 is a Stack-at-zero fault (always “0”).
In this case, as shown in 1) of the drawing, the Stack-at-zero fault of the address 7 cannot be detected while the Stack-at-one fault of the address 5 can be detected. That is, since the ECC circuit detects only the 1-bit error of the address 5 to correct the error, the BIST circuit determines a product to be nondefective even if the product is defective.
Subsequently, as shown in 2) of the drawing, writing/reading of inverted data [0101 . . . ] of the background data is executed in the testing target addresses 0, 1, 2, . . . 7.
In this case, the Stack-at-one fault of the address 5 cannot be detected while the Stack-at-zero fault of the address 7 can be detected. That is, since the ECC circuit detects only the 1-bit error of the address 7 to correct the error, the BIST circuit determines a product to be nondefective even if the product is defective.
Similarly, consideration is given to a case in which [1111 . . . ] is written as background data in all the addresses of the memory. Conditions are similar to those of the above example.
When 8-bit data is read out of the testing target addresses 0, 1, 2, . . . 7, as shown in 3) of the drawing, the Stack-at-one fault of the address 5 cannot be detected while the Stack-at-zero fault of the address 7 can be detected. That is, since the ECC circuit detects only the 1-bit error of the address 5 to correct the error, the BIST circuit determines a product to be nondefective even if the product is defective.
Subsequently, as shown in 4) of the drawing, writing/reading of inverted data [0000 . . . ] of the background data is executed in the testing target addresses 0, 1, 2, . . . 7.
In this case, the Stack-at-zero fault of the address 7 cannot be detected while the Stack-at-one fault of the address 5 can be detected. That is, since the ECC circuit detects only the 1-bit error of the address 5 to correct the error, the BIST circuit determines a product to be nondefective even if the product is defective.
Therefore, if the testing is executed by using the marching pattern even while there are Stack-at-2 bit faults in the testing target addresses 0, 1, 2, . . . 7, the ECC circuit cannot detect the Stack-at-2 bit faults simultaneously. Consequently, the BIST circuit mistakenly determines the product that has the Stack-at-2 bit faults in the testing target addresses 0, 1, 2, . . . 7 to be nondefective.
Incidentally, such a problem can be solved by increasing kinds of data patterns used for testing. That is, if there are Stack-at-faults a number of which exceeds the correction capability of the ECC circuit in the testing target addresses 0, 1, 2, . . . 7, testing can be carried out by using data patterns that enable sure detection of all the Stack-at-faults.
However, if the testing is carried out by increasing kinds of test patterns as described above, problems of increases in complexity and area of the BIST circuit, testing time etc., inevitably occur.